1. Field of the Invention
The present invention relates to an interrupt steering circuit for PCI (peripheral component interconnect) bus, and more specifically to an a PCI bus interrupt steering circuit for speeding up an interrupt processing.
2. Description of Related Art
In the PCI bus, by connecting one bit of an address/data bus (31:0) at a mother board as an IDSEL (initialization device select) signal, a device number of a device such as an expansion slot is determined. Therefore, unless this connection is changed, it is not possible to change the device number of the device.
On the other hand, as shown in FIG. 1, the PCI bus includes four interrupt signals "INTa0", "INTb0", "INTc0" and "INTd0", which are designated by Reference Numerals 10, 11, 12 and 13 in FIG. 1. Which of the four interrupt signals is used by devices on the PCI bus (namely, connected to expansion slots 1, 2, 3 and 4, respectively) is ambiguously determined by a given device number. These interrupt signals are outputted to interrupt signal lines 20, 21, 22 and 23, as shown in FIG. 1. In FIG. 1, Reference Numeral 30 designates an address/data bus (31:0), Reference Numeral 31 is an IDSEL signal to the expansion slot 1, Reference Numeral 32 is an IDSEL signal to the expansion slot 2, Reference Numeral 33 is an IDSEL signal to the expansion slot 3, Reference Numeral 34 is an IDSEL signal to the expansion slot 4, Reference Numeral 99 is a PCI bus. Incidentally, a control bus of the PCI bus is omitted in FIG. 1.
As mentioned above, since the PCI bus includes only four interrupt signals, when there exist five or more devices utilizing the interrupt, the interrupt signal is shared for example by using the interrupt signal in common as a low active signal (level sharing).
On the other hand, the device number of the device connected to the PCI bus is determined by the wiring on the mother board. In the PCI bus, accordingly, devices utilizing the same interrupt signal by the level sharing are ambiguously determined by the position of the devices mounted on the mother board.
In this case, since the interrupts from two or more level-shared devices is processed by one interrupt signal, a desired high-speed operation cannot be obtained in a system designed with an expectation of quickly executing the interrupt processing.
In addition, when one interrupt signal is shared in a level sharing manner by a plurality of devices frequently generating an interrupt request, it is in some case that the interrupt processing is not quickly executed. For example, consider the case that one interrupt signal is shared in a level sharing manner by four devices frequently generating an interrupt request. In this case, if the interrupt request is generated by one device, which of the four devices generates the interrupt request is discriminated by a software manner, and thereafter, a necessary processing is conducted for the device generating the interrupt request. The larger the number of devices sharing the same interrupt signal becomes, the longer the time required for this discrimination becomes. The increase of the processing time for the discrimination prevents the speed-up of the interrupt processing.
Now, if the following situation is considered, it would be understood that there exists a case that the four interrupt signals prescribed in the PCI cannot be efficiently utilized. For example, when four boards generating the interrupt on the PCI bus are mounted, the interrupt signal can be utilized more efficiently in the case that the four interrupt signals are used, than the case that only one interrupt signal is used. When eight boards generating the interrupt on the PCI bus are mounted, in order to efficiently utilize the interrupt signal, it is preferred that each one interrupt signal is shared by two boards, one of which frequently generates the interrupt request and the other of which does not so frequently generate the interrupt request.
In the PCI device, however, the interrupt signal to be used is determined by the mounting position of the device mounted on the mother board, a preferred operation cannot be obtained, differently from the case in which the frequency of the interrupt request is considered for each board, and a group of boards sharing the same interrupt signal in a level sharing manner are determined on the basis of the interrupt request frequency of respective boards.